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In `F33f`_`[computing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Computing]`_`f, `!Machine Check Architecture`! (`!MCA`!) is an `F33f`_`[Intel`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Intel]`_`f and `F33f`_`[AMD`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AMD]`_`f mechanism in which the `F33f`_`[CPU`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=CPU]`_`f reports hardware errors to the `F33f`_`[operating system`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Operating_system]`_`f.

`F33f`_`[Intel`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Intel]`_`f's P6 and Pentium 4 family processors, `F33f`_`[AMD`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AMD]`_`f's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, `F33f`_`[ECC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Error_detection_and_correction]`_`f errors, parity errors, `F33f`_`[cache`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=CPU_cache]`_`f errors, and `F33f`_`[translation lookaside buffer`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Translation_lookaside_buffer]`_`f errors. It consists of a set of model-specific registers (`F33f`_`[MSRs`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Model-specific_register]`_`f) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.`:cite-ref-1[`F5bf`_`[1`#cite-note-1]`_`f]

>>Contents

• `F0af`_`[See also`#see-also]`_`f

• `F0af`_`[References`#references]`_`f

• `F0af`_`[External links`#external-links]`_`f

-─

>>See also

• `F33f`_`[Machine-check exception`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Machine-check_exception]`_`f (MCE)

• `F33f`_`[High availability`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=High_availability]`_`f (HA)

• `F33f`_`[Reliability, availability and serviceability`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Reliability,_availability_and_serviceability]`_`f (RAS)

• `F33f`_`[Windows Hardware Error Architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Windows_Hardware_Error_Architecture]`_`f (WHEA)

>>References

`:cite-note-1`!1.`! `F0af`_`[↑`#cite-ref-1]`_`f "Machine Check Architecture". `*Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2`*. `F33f`_`[Intel`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Intel]`_`f Corporation. November 2018.

>>External links

• Microsoft's article on Itanium's MCA

• Linux x86 daemon for processing of machine checks

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